For higher density integration and higher performance of semiconductor integrated circuits (LSI) micro-processing techniques have recently been developed. A CMP (chemical mechanical polishing) method is one of such techniques. This method is often utilized in an interlevel insulation film planarizing step, a metal plug forming step and a burying step in an LSI fabrication process, particularly in a multilevel interconnection forming process (see, for example, U.S. Pat. No. 4,944,836).
Particularly, a recent trend of a wiring technique is to employ Cu or a Cu alloy (hereinafter referred to collectively as “Cu”) having a lower resistance instead of a conventionally used Al (aluminum) alloy to achieve higher performance of the LSIs. Cu has a lower resistivity (1.8 μΩcm) than the conventionally used Al-based alloy material. Further, the Al-based alloy typically has a melting point of 600° C., while Cu has a melting point of 1080° C. An electro-migration resistance and a stress-migration resistance have correlations with the melting point of the material. Therefore, Cu having a higher melting point is more reliable as an interconnection material than the Al-based alloy. In reality, the electro-migration resistance of Cu is higher by an order of magnitude than that of the aluminum-based alloy.
It is difficult to micro-process Cu by dry etching which is often used for formation of Al alloy interconnections. Therefore, a damascene method is employed in which Cu is deposited over an insulation film formed with a groove and a portion of the resulting Cu film formed outside the groove is removed by the CMP method to form a buried interconnection (see, for example, Japanese Unexamined Patent Publication No. HEI9(1997)-45782 published by Japanese Patent Office).
The Cu film is typically formed by forming a thin seed layer by a sputtering method or the like and then depositing Cu to a thickness of about several hundreds of nanometers by an electrolytic plating method. For suppression of diffusion of Cu into the insulation film at this time, a thin underlying film of a high melting point metal or a compound of the high melting point metal is generally formed over the insulation film after the formation of the groove and a hole in the insulation film. This is followed by the formation of the Cu buried interconnection (or the filling with Cu). After the formation of the Cu buried interconnection, the bottom and side walls of the groove and the hole are covered with the thin film (the aforementioned underlying film) of the high melting point metal or the high melting point metal compound (so-called barrier metal), so that bottom and side surfaces of the Cu buried interconnection contact the barrier metal.
Recently, it has been contemplated to use a low-k film having a lower dielectric constant as an interlevel insulation film. That is, an attempt is made to reduce parasitic capacitance occurring between interconnections by using a low-k film having a dielectric constant k of not higher than 3.5, for example, instead of a silicon oxide (SiO2) film having a dielectric constant k of about 4.2. Low-k film materials having a dielectric constant k of not higher than 2.5 are also under development. Most of these materials are porous materials having pores. A production method for a semiconductor device having a multilevel interconnection structure including such a low-k film (or a porous low-k film) and a Cu interconnection in combination is as follows.
FIGS. 10(a) to 10(e) are sectional views illustrating steps of the production method for the conventional semiconductor device having the multilevel interconnection structure including the low-k film and the Cu interconnection in combination. In FIGS. 10(a) to 10(e), a device forming step and the like are not shown.
As shown in FIG. 10(a), a first insulation film 221 is formed on a substrate 200 such as a silicon substrate by a CVD (chemical vapor deposition) method.
As shown in FIG. 10(b), a groove structure (an opening H) for formation of a Cu metal interconnection or a Cu contact plug is formed in the first insulation film 221 by a photolithography process and an etching process.
As shown in FIG. 10(c), a barrier metal film 240, a Cu seed film and a Cu film 260 are formed in this order over the first insulation film 221, and annealed at a temperature of 150° C. to 400° C. for about 30 minutes.
As shown in FIG. 10(d), a Cu interconnection is formed in the opening H (groove) by partly removing the Cu film 260 and the barrier metal film 240 by a CMP method.
As shown in FIG. 10(e), a silicon nitride film 277 is formed as a diffusion prevention film on a surface of the Cu film 260 and, if a multilevel Cu interconnection structure is to be formed, a second insulation film 281 is formed over the resulting substrate.
FIG. 11 is a sectional view of a semiconductor device having a multilevel interconnection structure.
Where the multilevel interconnection structure is formed as shown in FIG. 11, an independent first via layer having a via 93 for connecting a interconnection 91 of a first interconnection layer and an interconnection 92 of a second interconnection layer is provided between the first interconnection layer and the second interconnection layer. To provide a multilevel structure including a greater number of interconnection layers, the interconnection layers and via layers are alternately stacked.
Further, Japanese Unexamined Patent Publication (KOKAI) No. 9-45782 published by Japanese Patent Office discloses a technique for providing a fuse in a via layer for connection between interconnections provided in an overlying interconnection layer. A high melting point metal such as tungsten (W) or tantalum (Ta) or a silicide of the high melting point metal is used as a material for the fuse.
For higher density integration and higher speed operation of semiconductor devices, the interconnection structure is shifted from a single level structure to a multilevel structure. A semiconductor device having a metal interconnection structure including five or more interconnection layers has been developed and come into production. However, the higher density integration leads to a signal transmission delay attributable to so-called interconnect parasitic capacitance and interconnect resistance. The signal transmission delay attributable to the multilevel interconnection structure exerts significant influences on the higher speed operation of the semiconductor devices. In recent years, various measures against this problem have been taken.
In general, the signal transmission delay is expressed by a product of the interconnect parasitic capacitance and the interconnect resistance. For reduction of the interconnect resistance, the conventional Al interconnections are increasingly replaced with the lower resistance Cu interconnections. However, adjacent interconnections in each of the interconnection layers should be spaced a predetermined distance from each other, whether the interconnections be the Al interconnections or the Cu interconnections. As shown in FIG. 11, the interconnections should be formed at a minimum interconnection pitch A and spaced a distance B from each other. Therefore, even if a lower resistance material is employed in the conventional interconnection structure, the interconnections should be spaced a distance which is determined depending on the material. To provide the multilevel structure, the interconnection layers and the via layers should be alternately stacked, so that one via layer is required for each interconnection layer. Therefore, the total number of layers to be formed is double the number of the interconnection layers, making it difficult to increase the integration density.